I. Definition
As used herein, the phrase “group III-V” refers to a compound semiconductor that includes at least one group III element and at least one group V element. By way of example, a group III-V semiconductor may take the form of a III-Nitride semiconductor. “III-Nitride” or “III-N” refers to a compound semiconductor that includes nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)N), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N, gallium arsenide phosphide nitride (GaAsaPbN(1-a-b)), and aluminum indium gallium arsenide phosphide nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), for example. III-Nitride also refers generally to any polarity including but not limited to Ga-polar, N-polar, semi-polar, or non-polar crystal orientations. A III-Nitride material may also include either Wurtzitic, Zincblende, or mixed polytypes, and may include single-crystal, monocrystalline, polycrystalline, or amorphous structures. Gallium nitride or GaN, as used herein, refers to a III-Nitride compound semiconductor wherein the group III element or elements include some or a substantial amount of gallium, but may also include other group III elements in addition to gallium.
In addition, as used herein, the phrase “group IV” refers to a semiconductor that includes at least one group IV element such as silicon (Si), germanium (Ge), and carbon (C), and may also include compound semiconductors such as silicon germanium (SiGe) and silicon carbide (SiC), for example. Group IV also refers to semiconductor materials which include more than one layers of group IV elements, or doping of group IV elements to produce strained group IV materials, and may also include group IV based composite substrates such as silicon on insulator (SOI), separation by implantation of oxygen (SIMOX) process substrates, and silicon on sapphire (SOS), for example.
II. Background Art
A group III-V heterostructure field-effect transistor (group III-V HFET), such as group III-V high electron inability transistor (group III-V HEMT), can include III-Nitride films formed on a non-native substrate, such as group IV substrate (e.g., silicon). Epitaxial growth or deposition of the III-Nitride films on the non-native substrate often results in excessive wafer warpage and bow. Also, deleterious cracking and delamination of the III-Nitride films and/or the non-native substrate may occur. These undesirable results are typically caused by lattice constant mismatches between the III-Nitride films and the non-native substrate, as well as differences in coefficients of thermal expansion between the III-Nitride films and the non-native substrate.
Various approaches have been proposed to accommodate for stresses associated with depositing III-Nitride films on a non-native substrate. One such approach is the use of a compositionally graded transition layer as disclosed in U.S. Pat. No. 6,649,287, entitled “Gallium Nitride Materials and Methods,” and issued on Nov. 18, 2003, the disclosure of which is hereby incorporated fully by reference into the present application. Another approach is the use of compositionally graded transition layers as disclosed in U.S. Pat. No. 7,365,374, entitled “Gallium Nitride Material Structures Including Substrates and Methods Associated with the Same,” and issued on Apr. 29, 2008, the disclosure of which is hereby incorporated fully by reference into the present application.
An approach that has been proposed to accommodate for stresses associated with epitaxial growth of III-Nitride films on a non-native substrate is to modify the surface of the non-native substrate prior to the epitaxial growth. One such approach is to employ grid arrays or control joints formed in the non-native substrate of a wafer prior to growth of the III-Nitride films. These control joints can be aligned with saw streets for dies and prevent large area coalescence across an entirety of the wafer. The total stress built up across the wafer is thereby reduced, as disclosed in U.S. Pat. No. 8,557,681, entitled “III-Nitride Wafer Fabrication,” and issued on Oct. 15, 2013, the disclosure of which is hereby incorporated fully by reference into the present application.